1. Field
This document relates to a liquid crystal display and a method of controlling dot inversion thereof.
2. Related Art
An active matrix type liquid crystal display displays moving images using thin film transistors (hereinafter, referred to as “TFTs”) as switching elements. In comparison with a cathode ray tube (CRT), the liquid crystal display can have a smaller size. Thus, the liquid crystal display is used as displays in portable information devices, office equipment, computers, televisions, etc., and hence is fast replacing the cathode ray tube.
Liquid crystal cells of the liquid crystal display a picture image by changing transmittance by a potential difference between a data voltage supplied to a pixel electrode and a common voltage supplied to a common electrode. The liquid crystal display is generally driven by an inversion scheme of periodically inverting the polarity of the data voltage applied to the liquid crystal cell in order to prevent deterioration of the liquid crystal. When the liquid crystal display is driven by an inversion scheme, the liquid crystal display may have a low picture quality according to a correlation between the polarities of data voltages charged in the liquid crystal cells and the data voltages. This is because the polarity of data voltages charged in the liquid crystal cells are not balanced between the positive and negative polarities but either of the positive and negative polarities becomes dominant, and hence the common voltage applied to the common electrode is shifted. Once the common voltage is shifted, the reference potential of the liquid crystal cells is shifted, and this causes a viewer to feel flicker or smear on an image displayed on the liquid crystal display.
The polarity of the data voltages is determined by a polarity control signal POL output from a timing controller. Each source drive IC outputs a positive data voltage or negative data voltage in response to the polarity control signal POL. The vertical polarity of the data voltages output continuously through output channels of the source drive IC is determined according to the polarity control signal POL. The horizontal polarity of the data voltages output simultaneously from output channels of the source drive IC is determined by the polarity control signal POL. The horizontal polarity inversion cycle of the data voltages is determined according to a logic value of a voltage applied to an option terminal H—2DOT of each of the source drive ICs.
FIG. 1 is a view illustrating horizontal 1-dot inversion.
Referring to FIG. 1, the timing controller TCON commonly supplies a polarity control signal POL to source drive ICs, and each of the source drive ICs SDIC1 to SDIC3 supplies data voltages whose polarities are converted by horizontal 1-dot inversion to data lines of a liquid crystal display panel in response to the polarity control signal POL. In the horizontal 1-dot inversion, the polarities of odd-numbered data voltages supplied to odd-numbered data lines and the polarities of even-numbered data voltages supplied to even-numbered data lines are opposite to each other. Accordingly, in the horizontal 1-dot inversion, the polarities of data voltages simultaneously output from the source drive ICs SDIC1 to SDIC3 are inverted for each 1 dot (or for each liquid crystal cell). If the first logic value of the polarity control signal POL is high, the source drive ICs SDIC1 to SDIC3 output the odd-numbered data voltages of the first horizontal display line LINE#1 as positive data voltages (+) and the even-numbered data voltages of the first horizontal display line LINE#1 as negative data voltages (−) as shown in FIG. 1. In the next frame period, if the first logic value of the polarity control signal POL is inverted to low, the source drive ICs SDIC1 to SDIC3 output the odd-numbered data voltages of the first horizontal display line LINE#1 as negative data voltages (−) and the even-numbered data voltages of the first horizontal display line LINE#1 as positive data voltages (+).
FIG. 2 is a view illustrating horizontal 2-dot inversion.
Referring to FIG. 2, the timing controller TCON commonly supplies a polarity control signal POL to the source drive ICs, and each of the source drive ICs SDIC1 to SDIC3 supplies data voltages whose polarities are converted by horizontal 2-dot inversion to data lines of the liquid crystal display panel in response to the polarity control signal POL. In the horizontal 2-dot inversion, the polarities of data voltages supplied to (4i+1)-th and (4i+4)-th data lines (i is a positive integer) and the polarities of data voltages supplied to (4i+2)-th and (4i+3)-th data lines are opposite to each other. Accordingly, in the horizontal 2-dot inversion, the polarities of data voltages simultaneously output from the source drive ICs SDIC1 to SDIC3 are inverted every 2 dots. If the first logic value of the polarity control signal POL is high, the source drive ICs SDIC1 to SDIC3 output the (4i+1)-th and (4i+4)-th data voltages of the first horizontal display line LINE#1 as positive data voltages (+) and the (4i+2)-th and (4i+3)-th data lines of the first horizontal display line LINE#1 as negative data voltages (−) as shown in FIG. 2. In the next frame period, if the first logic value of the polarity control signal POL is inverted to low, the source drive ICs SDIC1 to SDIC3 output the (4i+1)-th and (4i+4)-th data voltages of the first horizontal display line LINE#1 as negative data voltages (−) and the (4i+2)-th and (4i+3)-th of the first horizontal display line LINE#1 as positive data voltages (+).
Each of the source drive ICs SDIC1 to SDIC3 receive the same polarity control signal as in FIGS. 1 and 2 and inverts the polarity of data voltages. However, in the horizontal 2-dot inversion, in the case that the remainder left after dividing the number of output channels of the source drive IC by 4 is not zero, for example, the number of output channels of the source drive IC is 630 or 690, the horizontal polarity of the data voltages is inverted by vertical 1-dot inversion at the boundaries between the source drive ICs as indicated by dotted circles in FIG. 2. In this case, a luminance difference appears in a pixel array section driven by the horizontal 2-dot, inversion and a pixel array section between the source drive ICs driven by the horizontal 1-dot inversion. Accordingly, in the horizontal 2-dot inversion driving scheme as shown in FIG. 2, a boundary noise is observed between the source drive ICs. Such a boundary noise becomes severe when an FRC correction value is added to data in the process of applying frame rate control (FRC) to increase picture quality.
The present inventor proposed, in Koran Patent Application No. 10-2008-0032638 filed on Apr. 8, 2008, a technique for minimizing common voltage shift in any weak pattern and minimizing flickering, color distortion, etc. by analyzing a weak pattern in an input image and adaptively selecting a horizontal 1-dot inversion scheme or a horizontal 2-dot inversion scheme according to the type of the weak pattern to drive a liquid crystal display panel. To further increase the effect of display quality improvement of this technique, a boundary noise that may appear in the horizontal 2-dot inversion has to be eliminated.